Review on Reversible Radix-2 FFT using Reversible Gate and Different Adder
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Abstract
Reversible computing has emerged as a promising approach for designing low-power and energy-efficient digital circuits by minimizing information loss and reducing heat dissipation. In Very Large-Scale Integration (VLSI) systems, Reversible Logic Gates have gained considerable attention due to their potential applications in quantum computing, nanotechnology, digital signal processing (DSP), and low-power hardware architectures. Among DSP algorithms, the Radix-2 Fast Fourier Transform (FFT) is one of the most widely used techniques for efficient computation of the Discrete Fourier Transform (DFT), playing a vital role in wireless communication, image processing, biomedical engineering, radar, and multimedia applications. The performance of a reversible Radix-2 FFT architecture is largely influenced by the efficiency of the reversible butterfly unit and the reversible adder employed during arithmetic operations.
This review presents a comprehensive analysis of Reversible Radix-2 FFT architectures implemented using various reversible logic gates, including Feynman Gate (FG), Fredkin Gate (FRG), Toffoli Gate (TG), Peres Gate (PG), HNG Gate, TSG Gate, and BKG Gate, along with different reversible adder designs such as Ripple Carry Adder (RCA), Carry Look-Ahead Adder (CLA), Carry Save Adder (CSA), Carry Select Adder (CSLA), and Modified Carry Select Adder (MCSLA). The review compares existing architectures based on important design metrics, including quantum cost, garbage outputs, constant inputs, propagation delay, power consumption, silicon area, and hardware complexity. Furthermore, recent optimization techniques aimed at reducing quantum cost and improving computational efficiency are critically discussed.
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