VHDL Implementation of Reversible Arithmetic Logic Unit using Bidirectional Gate
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Abstract
Reversible computing is a promising approach to addressing the challenges of energy dissipation and efficiency in modern digital systems. This study explores the design and VHDL implementation of a Reversible Arithmetic Logic Unit (RALU) using bidirectional gates. The proposed RALU architecture integrates arithmetic and logical operations with reversibility, ensuring minimal power loss and enhanced computational efficiency. By leveraging the unique properties of bidirectional gates, the design achieves reduced quantum cost, gate count, and propagation delay compared to traditional ALU designs. The VHDL implementation provides a hardware description that can be synthesized and tested on FPGA platforms, offering insights into its practical applicability in low-power and quantum computing environments. Simulation results validate the correctness and performance of the proposed RALU, demonstrating its potential for use in advanced computing systems, including cryptography, quantum processors, and energy-efficient embedded systems. In this paper, the two novel 4*4 reversible logic gates (HNG and PFAG) are used with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. The proposed RALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE software.
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