Ravindra Kumar Ahirwar, Prof. Suresh S. Gawande. VHDL Implementation of Reversible Arithmetic Logic Unit using Bidirectional Gate. IJARMT [Internet]. 2025 Jan. 20 [cited 2025 Jul. 25];2(1):110-21. Available from: https://ijarmt.com/index.php/j/article/view/50