Teepu Sultan,Prof. Suresh S. Gawande. “VLSI Architecture for FIR Filter Using Radix-4 Booth Multiplier and CBL Adder”. International Journal of Advanced Research and Multidisciplinary Trends (IJARMT) 2, no. 1 (February 20, 2025): 390–402. Accessed January 14, 2026. https://ijarmt.com/index.php/j/article/view/110.